View SLE25C160-DP_6768430.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

standard eeprom ics slx 25c160 16 kbit (2048 8 bit) serial cmos-eeprom with serial peripheral interface (spi) synchronous bus data sheet preliminary 1999-03-15
page protection mode? is a trademark of siemens ag. edition preliminary 1999-03-15 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. slx 25c160 revision history: current version: preliminary 1999-03-15 previous version: 199-02-02 page (in previous version) page (in current version) subjects (major changes since last revision) 23 23 tex t changed to the write or erase cycle is finished after 2.5 ms (typical) 14 14 figure 7 has changed 19 19 figure 11 has changed
p-dip-8-4 p-dip-8-3 p-dso-8-2 p-dso-8-1 16 kbit (2048 8 bit) serial cmos eeproms, serial peripheral interface (spi) synchronous bus slx 25c160 semiconductor group 3 preliminary 1999-03-15 preliminary 1 overview 1.1 features ? serial peripheral interface (spi) compatible, supports spi modes 0,0 and 1,1 ? page protection mode tm for protecting the eeprom against unintended data changes (slx 25c160.../p types only) ? low power cmos ? clock frequency up to 2.1 mhz ? v cc = 2.7 to 5.5 v operation ? 32-byte page mode ? write protect (wp ) pin and write disable instruction for both hardware and software data protection ? block write protection - protect 1/4, 1/2 or entire array ? filtered inputs for noise suppression with schmitt trigger ? high programming flexibility C internal programming voltage C self timed write cycle including erase (5 ms typical) for up to 32 bytes C byte-write and page-write programming, between 1 and 32 bytes ? high reliability C endurance 10 6 cycles 1) C data retention 40 years 1) C esd protection > 4000 v on all pins ? 8 pin dip/dso packages ? available for extended temperature ranges C industrial: - 40 c to + 85 c C automotive: - 40 c to + 125 c ( - 40 c to + 150 c on request) 1) values are temperature dependent, for further information please refer to your siemens sales office.
slx 25c160 semiconductor group 4 preliminary 1999-03-15 other types are available on request: C temperature range (C 40 c o + 150 c) C packages (tssop-8, die, wafer delivery) 1.2 pin configuration figure 1 pin configuration (top view) table 1 ordering information type ordering code package temperature voltage sla 25c160-d sla 25c160-d/p on request p-dip-8-3 C 40 c + 85 c 2.7 v 5.5 v sla 25c160-s sla 25c160-s/p on request p-dso-8-2 C 40 c + 85 c 2.7 v 5.5 v sle 25c160-d sle 25c160-d/p on request p-dip-8-3 C 40 c + 125 c 2.7 v 5.5 v sle 25c160-s sle 25c160-s/p on request p-dso-8-2 C 40 c + 125 c 2.7 v 5.5 v p-dip-8-3 5 4 36 27 18 ss wp v cs so sck si hold v cc iep02585 p-dso-8-2 si wp 5 4 v cc iep02586 36 27 18 sck hold ss v so cs
slx 25c160 semiconductor group 5 preliminary 1999-03-15 pin definitions and functions. pin description serial input (si) the si pin is an input and used to clock all instructions, byte addresses and data into the device. input data is latched on the rising edge of the serial clock. serial output (so) the so pin is an output and used to shift data out of the device. data is clocked out by the falling edge of the serial clock. serial clock (sck) the sck pin is an input and used to synchronize the communication between the master and the eeprom. table 2 pin no. symbol function 1cs chip select input 2 so serial output 3wp write protection input 4 v ss ground 5 si serial input 6 sck serial clock input 7 hold hold input 8 v cc supply voltage
slx 25c160 semiconductor group 6 preliminary 1999-03-15 chip select (cs ) the cs pin is an input and used to enable or disable the device. when the cs pin is low, the device is enabled. when the cs pin is high, the device is disabled and, if no internal programming cycle is in process, forced into the standby mode. after power up, a high-to-low transition of the cs pin is required prior to the start of any operation. a low-to-high transition of the cs pin after a valid write or erase command starts an internal programming cycle. independent of the cs pin an already started programming cycle will be finished and then the device forced into the standby mode. when the device is deselected, so goes to the high impedance state, allowing multiple parts to share the same spi bus. write protect (wp ) the wp pin is an input and used to enable or disable write operations to the status register. when the wp pin is high, write operations to the status register are allowed. when the wp pin is low, all write operations to the status register are disabled, but write operations to the memory are not effected. if the internal programming cycle has already been initiated, a high to low transition of the wp pin will have no influence on the programming cycle. note: the function of the wp pin can be blocked by setting the wpen (w rite p rotect en able) bit in the status register to 0 (refer to chapter 4 status register). in this case write operations to the status register are possible independent of the status of the wp pin. when the wpen bit is 1, it cannot be changed back to 0, as long as the wp pin is held low. hold (hold ) the hold pin is an input. when the device is selected with cs pin low, the hold pin can be used to pause the serial communication with the master and to continue the communication later without resetting the serial sequence. to pause the communication the hold pin must be brought low while the sck pin is low. inputs to the si pin will be ignored and the so pin is in the high impedance state. sck may still toggle during hold . to continue the communication the hold pin must be brought high while the sck pin is low. the hold pin must be held high any time this function is not being used.
slx 25c160 semiconductor group 7 preliminary 1999-03-15 2 description slx 25c160 is a serial electrically erasable and programmable read only memory (eeprom), organized as 2048 8 bit. the data memory is divided into 64 pages. up to 32 bytes of a page can be programmed simultaneously. the device is accessed via a s erial p eripheral i nterface (spi) compatible bus (spi modes 0,0 and 1,1). the required bus signals are clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through the chip select input (cs ), allowing any number of devices to share the same bus. for applications with high security requirements against unintended data changes devices with page protection mode tm (slx 25c160.../p types only, refer to chapter 7 ) are available. low voltage design permits operation down to 2.7 v with low active and standby currents. all devices have a minimum endurance of 10 6 erase/write cycles 1) . the device operates with a maximum clock frequency of 2.1 mhz, a voltage range of v cc = 2.7 5.5 v and is available in two temperature ranges for industrial and automotive applications. the device is available in eight-pin dip and dso packages; additionally the device may be purchased in die or wafer format. figure 2 block diagram 1) values are temperature dependent, for further information please refer to your siemens sales office. ieb02621 status register i/o control logic logic address programming control hv generator x decoder page protection page logic y decoder eeprom dout/din wp cs sck si so hold v cc v ss
slx 25c160 semiconductor group 8 preliminary 1999-03-15 3 spi bus characteristics access to the slx 25c160 device is given via the spi bus. this bus consists of three wires: sck for clock, si for input data from the master to the device and so for output data from the device to the master. the protocol is master/slave oriented, where the serial eeprom always takes the role of a slave. the device is selected via the cs pin. figure 3 bus configuration master device that initiates the transfer of data and provides the clock for transmit and receive operations. mosi = master output slave input miso = master input slave output slave device addressed by the master, capable of receiving and transmitting data. transmitter/ receiver the slx 25c160 has separate pins for data transmission (so) and reception (si). ieb02622 data out (mosi) data in (miso) serial clock (spi ck) so si sck cs ss0 slaves: so sck cs si so cs sck si cs sck so si ss1 ss2 ssn master: microcontroller eeproms
slx 25c160 semiconductor group 9 preliminary 1999-03-15 spi modes 0,0 and 1,1 spi modes 0,0 and 1,1 means for the slave that the input data is latched on the rising edge of the serial clock and the output data clocked out by the falling edge of the serial clock. msb the most significant bit (msb) is the first bit transmitted and received. invalid instruction if an invalid instruction is received, the data will be ignored by the device, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication.
slx 25c160 semiconductor group 10 preliminary 1999-03-15 4 status register slx 25c160 has a status register indicating the actual status of the device. read operations are allowed to all bits of the status register via the command byte rdsr (r ead s tatus r egister), whereas write operations are only allowed to bit 2-3 (bp0,bp1) and bit 7 (wpen) via the command byte wrsr (wr ite s tatus r egister). bit 1 (wel) indicates whether the device is enabled or disabled for write operations. its status can only be changed via the command bytes wren (wr ite en able, bit 1 = 1) and wrdi (wr ite di sable, bit 1 = 0). all write operations to the status register and to the entire memory has to be preceded by the command byte wren. the definition of the status register is shown in table 3 . note: bit 0-7 are read as 1 during an internal programming cycle. table 3 definition of the status register bit name definition 0 wip w rite i n p rocess: 0 indicates the device is ready. 1 indicates that a programming cycle is in process (bit 0: read only). 1 wel w rite e nable l atches: 0 indicates the device is not enabled for write operations. 1 indicates the device is enabled for write operations (bit 1: read only). 2 bp0 the b lock p rotect b its indicate which blocks are currently write protected (see table 6 ) (bits 2/3: read/write). 3 bp1 4 x these bits are not used and always read as 1 (bits 3/4: read only). 5x 6 ppa slx 25c160... (without page protection mode tm ): no special function, always read as 1 (bit 6: read only). slx 25c160.../p (with page protection mode tm , refer to chapter 7 ): 0 indicates a write or erase operation of the ppm-bits is finished successfully. 1 indicates a write or erase operation of the ppm-bits failed or is still in process. note: after power-up ppa is read as 1 (bit 6: read only). 7 wpen w rite p rotect en able bit: 0 blocks the function of the wp pin. independent of the wp pin the user can write to the status register. 1 enables the function of the wp pin (refer to chapter 1 pin description) (bit 7: read/write).
slx 25c160 semiconductor group 11 preliminary 1999-03-15 4.1 write enable and disable instructions for status register and memory wr ite en able (wren) the device will power up in the write disable state when v cc is applied. all programming commands for the status register and for the memory must therefore be preceded by the write enable command byte wren. this command sets the wel bit to 1. after the cs line is pulled low to select the device, the command byte wren is transmitted via the si line. after the transmission of the command byte, the cs pin has to be driven high. note: after a programming command to the status register or to the memory, the device is automatically returned to the write disable state (wel = 0). figure 4 write enable (wren) sequence table 4 write enable and disable instructions command byte definition function b7 b6 b5 b4 b3 b2 b1 b0 wren 00000110 set the write enable latch (enable write operations). wrdi 00000100 reset the write enable latch (disable write operations). ied02623 command byte (wren) so high impedance cs sck si 0 00 012 1 00 34 6 57 1 0
slx 25c160 semiconductor group 12 preliminary 1999-03-15 wr ite di sable (wrdi) to protect the device against inadvertent writes, the command byte wrdi sets the wel bit to 0 and therefore all programming modes are disabled. after the cs line is pulled low to select the device, the command byte wrdi is transmitted via the si line. after the transmission of the command byte the cs pin has to be driven high. figure 5 write disable (wrdi) sequence 4.2 write operation to the status register wr ite s tatus r egister (wrsr) the command byte wrsr allows the user to change the status of the bp0, bp1 and wpen bits in the status register. all other bits in the status register are for read only. in order to start a write operation to the status register, two separate command bytes must be executed. first, the device must be write enabled via the write enable command byte wren. then the write status register command byte wrsr can be executed. writing to the status register via the si input requires the following sequence. after the cs line is pulled low to select the device, the command byte wrsr is transmitted via table 5 write instruction for the status register command byte definition function b7 b6 b5 b4 b3 b2 b1 b0 wrsr 00000001 write status register ied02624 command byte (wrdi) so high impedance cs sck si 0 00 012 1 00 34 6 57 0 0
slx 25c160 semiconductor group 13 preliminary 1999-03-15 the si line followed by the status register byte to be programmed (bit 6-4 and 1-0 are dont care bits). programming will start after the cs pin is brought high. figure 6 write to status register (wrsr) sequence memory blocks can be protected using bp0 and bp1 according to table 6 . data protected in this manner can be read only. the command byte wrsr also allows the user to enable or disable the function of the wp pin through the use of the write protect enable bit wpen. when wpen is 0 all changes to bp0, bp1 and wpen are allowed independent of the status of the wp pin. wpen = 1 enables the function of the wp pin (refer to chapter 1 pin description). table 6 block write protection bits bp1 bp0 array address protected protected block 00- 0 0 1 $600-$7ff upper 1/4 1 0 $400-$7ff upper 1/2 1 1 $000-$7ff all ied02637 command byte (wrsr) so high impedance cs sck si 0 00 012 0 00 1 34 6 57 10 89 12 msb wpen x bp1 data to status register xx bp0 x 15 13 14 lsb x 11 0
slx 25c160 semiconductor group 14 preliminary 1999-03-15 4.3 read operation to the status register r ead s tatus r egister (rdsr) the command byte rdsr provides read access to the status register. the status register can be read at any time, even during an internal programming cycle. reading the status register via the so output requires the following sequence. after the cs line is pulled low to select a device, the rdsr command byte is transmitted via the si line. the content of the status register is then shifted out onto the so line. the cs pin should be driven high after data come out. note: during an internal programming cycle bit 0-7 of the status register are read as 1. figure 7 read from status register (rdsr) sequence table 7 read instruction for the status register command byte definition function b7 b6 b5 b4 b3 b2 b1 b0 rdsr 00000101 read status register ied02638 command byte (rdsr) so high impedance cs sck si 0 00 012 1 00 1 34 6 57 10 89 12 msb wpen ppa pb1 data out of status register 11 pb0 wel 13 14 lsb wip 11 0
slx 25c160 semiconductor group 15 preliminary 1999-03-15 5 write operations in order to start a write operation, two separate operations must be executed. first, the device must be write enabled via the write enable command byte wren. then the write operation can be executed. either one byte (byte write) or up to 32 byte (page write) can be modified in one programming procedure. during an internal programming cycle, all commands will be ignored except the command byte rdsr (read status register). note: write operations to the memory can only be executed to blocks that are not write protected by the status register bits bp0 and pb1 and to pages that are not write protected by a page protection bit ( slx 25c160 .../p only, refer to chapter 7 ). table 8 write instruction command byte definition function b7 b6 b5 b4 b3 b2 b1 b0 write 00000010 write data to memory array beginning at selected address.
slx 25c160 semiconductor group 16 preliminary 1999-03-15 5.1 byte write a write operation requires the following sequence. after the cs line is pulled low to select the device, the command byte write is transmitted via the si line followed by the byte address (a15-a11 are dont care bits, a10-a0) and the data (d7-d0) to be programmed. programming will start after the cs pin is brought high. the ready/busy status of the device can be determined by initiating a read to the status register with rdsr. if wip = 0. the programming cycle is finished. after execution of the command byte write the eeprom is automatically returned to the write disable state. figure 8 byte write sequence ied02639 eeprom address command byte (write) so high impedance cs sck si 0 00 012 0 00 1 0 34 6 57 a13 msb a15 a14 a3 10 89 20 msb d7 d6 d3 data byte d5 d4 d2 d1 a0 lsb a2 a1 23 21 22 24 25 28 26 27 29 30 lsb d0 31
slx 25c160 semiconductor group 17 preliminary 1999-03-15 5.2 page write the page write procedure is the same as the byte write procedure up to the first data byte. in a page write procedure however, the eeprom address bytes is followed by a sequence of one to a maximum of 32 data bytes with new data to be programmed. if more than 32 bytes of data are transmitted, the address counter will roll over and the previously transmitted data will be overwritten, i.e. only the last 32 transmitted bytes will be programmed. programming will start after the cs pin is brought high. the ready/busy status of the device can be determined by initiating a read to the status register with rdsr. if wip = 0. the programming cycle is finished. after execution of the command byte write the eeprom is automatically returned to the write disable state. figure 9 page write sequence d2 d4 data byte n+1 high impedance sck si so d6 d5 d7 msb msb d7 d0 d1 d3 d2 lsb d3 d5 d4 d6 data byte n+2 lsb d0 d5 d0 d1 d7 lsb msb d2 d3 d1 d4 data byte n+31 ied02640 a3 20 45 2 35 high impedance command byte (write) so cs 32 33 34 cs sck si 00 01 40 36 37 38 39 41 42 43 44 0 0000 1 3456 a15 msb a14 a13 8 7 9 10 30 279 274 46 47 48 276 275 277 278 25 d6 eeprom address a2 a1 a0 d7 21 22 23 24 d5 26 27 28 29 lsb 31 d4 d2 d3 d1 d0 lsb msb data byte n
slx 25c160 semiconductor group 18 preliminary 1999-03-15 6 read operations either one byte (byte read) or any number of bytes up to the whole memory (sequential read) can be read in one sequence. 6.1 byte read reading the eeprom via the so output requires the following sequence. after the cs line is pulled low to select the device, the read command byte is transmitted via the si line followed by the address to be read (a15-a11 are dont care bits, a10-a0). the data (d7-d0) at the specified address are then shifted out onto the so line. during this time, any data on the si line will be ignored. if only one byte is to be read, the cs line should be driven high after data come out. figure 10 read byte sequence table 9 read instruction command byte definition function b7 b6 b5 b4 b3 b2 b1 b0 read 00000011 read data from memory array beginning at the selected address. ied02641 eeprom address command byte (read) so high impedance cs sck si 0 00 012 0 00 11 34 6 57 a13 msb a15 a14 a3 10 89 20 d7 d6 d3 data byte d5 d4 d2 d1 a0 lsb a2 a1 23 21 22 24 25 28 26 27 29 30 d0 msb lsb
slx 25c160 semiconductor group 19 preliminary 1999-03-15 6.2 sequential read the sequential read procedure is the same as the byte read procedure up to the first data byte is shifted out on the so line. the read can be continued since the byte address is automatically incremented and data will continue to be shifted out. the read sequence is terminated by pulling up the cs line. note: when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read out in one continuous read cycle. figure 11 sequential read sequence d2 data byte n+2 d4 data byte n+1 msb si so sck d7 d5 d6 msb lsb d7 d3 d2 d1 d0 d6 d5 d4 d3 d0 lsb lsb msb d5 d1 d0 d7 d6 data byte n+x d4 d3 d2 d1 ied02642 20 a3 45 eeprom address 2 0 35 command byte (read) high impedance cs so 32 34 33 si sck cs 00 01 40 36 37 38 39 41 42 43 44 7 1 000 1 3456 a15 msb a14 a13 8910 30 d1 d6 46 47 48 49 d7 data byte n d5 d4 d2 d3 25 lsb a2 a1 a0 21 22 23 24 26 27 28 29 d0 31 lsb msb
slx 25c160 semiconductor group 20 preliminary 1999-03-15 7 page protection mode tm the page protection mode is supported by the slx 25c160.../p types only. for example sla 25c160-d/p has the same functionality as sla 25c160-d enhanced by page protection mode. each page (32 bytes) in the data memory can be protected against unintended data changes by an associated protection bit. the protection bit memory consists of an additional eeprom of 64 bit ( figure 12 ). data in the data memory can be modified only if the assigned protection bit is erased (logical state 1). after writing the data bytes to a page, the protection is achieved by writing the associated protection bit (logical state 0). further changes of data within a protected page is possible only after erasing the protection bit. figure 12 data page and assigned protection memory a special procedure to write or erase a protection bit guarantees proper activation or deactivation of page protection. for protection bit write or erase, all 32 data bytes of the respective page have to be entered for verification. the data then are compared internally with the data to be protected. in case of identity the protection bit is written or erased correspondingly. 1 023 . . . . . . 0 1 2 3 n page 0 page 1 page 2 page 3 page n byte bit data memory area protection bit memory area ied02521 31 . . . . . .
slx 25c160 semiconductor group 21 preliminary 1999-03-15 7.1 protection bit handling the bits of the protection memory can be addressed directly for reading or programming. a protection bit address corresponds to the lowest address within the respective page (a15-a11 are dont care bits, a10-a5, a4 to a0 = 0). the status of each protection bit is sensed internally. a written state (0) prevents programming in the associated page. if an already protected memory page is accidentally addressed for programming, the programming procedure is suppressed. for devices with page protection mode, an additional instruction set for addressing and manipulation of protection bits is implemented. for protection bit handling there are three additional command bytes for write, erase and read of a protection bit. these three command bytes are listed below ( table 10 ). table 10 instructions for protection bit manipulation command byte definition function b7 b6 b5 b4 b3 b2 b1 b0 wrpb 00100010 write page protection bit of selected page. erpb 00110010 erase page protection bit of selected page. rdpb 00010011 read page protection bit of selected page.
slx 25c160 semiconductor group 22 preliminary 1999-03-15 7.2 protection bit write and erase for writing or erasing a protection bit, the data of the respective page have to be known by the master. the master has to present the page data as a reference for comparison by the eeprom. a successful comparison is necessary in order to change the status of the protection bit. the data of the page are not effected by the write or erase procedure of the protection bit. the spi b us protocol is shown in figure 13 for protection bit write and in figure 14 for protection bit erase. figure 13 sequence for protection bit write a write or erase operation to a page protection bit requires the following sequence. after the cs line is pulled low to select the device, the command byte wrpb for protection bit write (or erpb for protection bit erase) is transmitted via the si line followed by the address bytes (a15-a11 are dont care bits, a10-a5, a4 to a0 = 0).the address of the protection bit corresponds to the address of the first byte of the page to protect (or unprotect). the address bytes are followed by 32 parameter bytes identical to the 32 data bytes of the page to be protected or unprotected. the data of the first entered byte must be identical to the data byte stored at the lowest address of the current page. d2 d4 data byte 1 high impedance sck si so d6 d5 d7 msb msb d7 d0 d1 d3 d2 lsb d3 d5 d4 d6 data byte 2 lsb d0 d5 d0 d1 d7 lsb msb d2 d3 d1 d4 data byte 32 ied02643 12 37 2 27 high impedance command byte (wrpb) so cs 24 25 26 cs sck si 00 01 32 28 29 30 31 33 34 35 36 0 1 000 1 3456 msb 8 7 9 10 11 22 38 39 40 17 eeprom address 13 14 15 16 a10 18 19 20 21 a8 a9 23 xxxxx 0 a7 a6 a5 0 0 00 lsb 275 274 276 277 279 278
slx 25c160 semiconductor group 23 preliminary 1999-03-15 the other 31 bytes have to be identical to the bytes stored in ascending address order within the same page. programming will start after the cs pin is brought high. . figure 14 sequence for protection bit erase for a successful programming of a protection bit, three conditions have to be fulfilled. 1. the page must be located within a block which is not protected by the status register bits pb0 and pb1. 2. the device must be write enabled via the write enable instruction (wren), before the write (wrpb) or erase (erpb) instruction can be executed. 3. all 256 bits of a page have to be verified successfully. a successful programming is indicated by the eeprom by setting the ppa-bit to 0 in the status register. the write or erase cycle is finished after 2.5 ms (typical). d2 d4 data byte 1 high impedance sck si so d6 d5 d7 msb msb d7 d0 d1 d3 d2 lsb d3 d5 d4 d6 data byte 2 lsb d0 d5 d0 d1 d7 lsb msb d2 d3 d1 d4 data byte 32 ied02644 x 12 37 2 27 high impedance command byte (erpb) so cs 24 25 26 cs sck si 00 01 32 28 29 30 31 33 34 35 36 0 11 00 1 3456 x msb xxx 8 7 9 10 11 22 279 274 38 39 40 276 275 277 278 17 a6 eeprom address a10 a9 a8 a7 13 14 15 16 a5 000 18 19 20 21 0 lsb 0 23
slx 25c160 semiconductor group 24 preliminary 1999-03-15 7.3 protection bit read the status of the protection bit can be requested by the master. the byte sequence for protection bit read is shown in figure 15 . figure 15 byte sequence for protection bit read to read the status of a protection bit the device must be selected with a high to low transition of the cs pin, then the rdpb command has to be send followed by the basis address of the respective page (a15-a11 are dont care bits, a10-a5, a4 to a0 = 0). the first bit (msb) of the transferred byte indicates the status of the protection bit of the addressed page. the other 7 bits are not valid. the page protection status is indicated as follows: protection bit = 1: the page protection mode tm is deactivated. protection bit = 0: the page protection mode tm is activated and data in the associated page are protected against changes. x x page n sck si so x x pb msb msb pb x x x x lsb x xx x page n+1 lsb x x x x pb lsb msb x x x x page n+x ied02645 x 12 37 2 27 high impedance command byte (rdpb) so cs 24 25 26 cs sck si 00 01 32 28 29 30 31 33 34 35 36 1 0 1 00 1 3456 x msb xxx 8 7 9 10 11 22 38 39 40 17 a6 eeprom address a10 a9 a8 a7 13 14 15 16 a5 000 18 19 20 21 0 lsb 0 23 pb = protection bit
slx 25c160 semiconductor group 25 preliminary 1999-03-15 to stop the transmission the device has to be deselected with a low to high transition of the cs pin. if not, the address counter is incremented automatically and the device will send the protection bit status of the next page. if the address of the highest page is reached, the address counter will roll over to the address of the lowest page.
slx 25c160 semiconductor group 26 preliminary 1999-03-15 8 electrical characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. 8.1 absolute maximum ratings stresses above those listed here may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 8.2 dc characteristics table 11 parameter limit values units operating temperature range 1 (industrial) range 2 (automotive) C 40 to + 85 C 40 to + 125 (C 40 to + 150 on request) c c c storage temperature C 65 to + 150 c supply voltage C 0.3 to + 7.0 v all inputs and outputs with respect to ground C 0.3 to v cc + 0.5 v esd protection (human body model) > 4000 v table 12 parameter symbol limit values units test condition min. typ. max. supply voltage v cc 2.7 5.5 v supply current 1) (read) i cc 0.5 ma v cc = 5 v; f c = 2.1 mhz supply current 1) (write) i cc 1ma v cc = 5 v; f c = 2.1 mhz standby current 2) i sb 3 m a v cc = 5 v
slx 25c160 semiconductor group 27 preliminary 1999-03-15 8.3 ac characteristics input leakage current i li 0.1 3 m a v in = v cc or v ss output leakage current i lo 0.1 3 m a v out = v cc or v ss input low voltage v il C 0.3 0.3 v cc v input high voltage v ih 0.7 v cc v cc + 0.5 v output low voltage v ol 0.4 v i ol = 3 ma; v cc = 5 v i ol = 2.1 ma; v cc = 3 v input/output capacitance (si/so) c i/o 8 3) pf v in = 0 v; v cc = 2.7 v input capacitance (other pins) c in 6 3) pf v in = 0 v; v cc = 2.7 v 1) the values for i cc are maximum peak values 2) valid over the whole temperature range 3) this parameter is characterized only table 13 parameter symbol limit values v cc = 2.7 - 5.5 v units min. typ. max. sck clock frequency f sck 0 2.1 mhz cycle time t cyc 475 ns cs lead time t lead 250 ns cs lag time t lag 250 ns clock high time t wh 200 ns clock low time t wl 200 ns data setup time t su 100 ns data hold time t h 100 ns table 12 (contd) parameter symbol limit values units test condition min. typ. max.
slx 25c160 semiconductor group 28 preliminary 1999-03-15 8.4 erase and write characteristics clock rise time t ri 2 m s clock fall time t fi 2 m s hold setup time t hd 100 ns hold hold time t cd 100 ns cs deselect time t cs 500 ns output disable time t dis 250 ns output valid from clock low t v 200 ns output hold time t ho 0ns output rise time t 1) ro 200 ns output fall time t 1) fo 200 ns rising edge of hold to output out of z t lz 100 ns falling edge of hold to output on z t hz 100 ns si/so and sck spike suppression time at constant inputs t l 50 ns 1) this parameter is characterized only table 14 parameter symbol limit values v cc = 2.7-5.5 v units typ. max. erase + write cycle (per page) t wc 58ms erase page protection bit 2.5 4 ms write page protection bit 2.5 4 ms table 13 (contd) parameter symbol limit values v cc = 2.7 - 5.5 v units min. typ. max.
slx 25c160 semiconductor group 29 preliminary 1999-03-15 8.5 timing diagrams figure 16 bus timing for serial input figure 17 bus timing for serial output msb in so si high impedance lsb in iet02625 cs sck t su lead t t h fi t t ri t lag t cs iet02626 t so si lsb in addr. v cs sck t msb out ho cyc t dis t wl lsb out t wh t lag t
slx 25c160 semiconductor group 30 preliminary 1999-03-15 figure 18 hold timing hold si iet02627 cs so sck cd t t hd t hz lz t t hd t cd
slx 25c160 semiconductor group 31 preliminary 1999-03-15 9 package outlines sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. smd = surface mounted device dimensions in mm p-dip-8-3 (plastic dual in-line package) gpd05696 gps05473 p-dso-8-2 (plastic dual small outline package)

▲Up To Search▲

Price & Availability of SLE25C160-DP

	To Download SLE25C160-DP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .